Description Of The Prior Art
The technology of producing semiconductor devices has been continually pressured to increase effective device densities in order to remain cost competitive. As a result, VLSI and ULSI technologies have entered the sub-micron realm of structural dimension and now are approaching physical limits in the nanometer feature size range. In the foreseeable future absolute atomic physical limits will be reached in the conventional two-dimensional approach to semiconductor device design. Traditionally, Dynamic Random Access Memory (DRAM) designers have faced the severest of challenges in advancing technologies. For example, designers of 64K DRAMs were perplexed to learn that a practical physical limit to charge capacity of storage capacitors had already been reached due to the minimum charge necessary to sense signals in the presence of environmental particulate radiation inherently present in fabrication materials. Storage capacitors in the range of 50 femtofarads are now considered to be a physical limit. From a practical view, this limitation prevented the scaling of DRAM capacitors. Reduction of the surface area of a semiconductor substrate utilized by the storage capacitor has been severely restricted. Due to decreases in the thickness of capacitor materials, existing 1 Megabit (1 Mb) DRAM technologies continue to enjoy the freedom of planar device and circuit design. Beginning with 4 Mb DRAMs the world of three-dimensional design has been explored to the extent that the simple single device/capacitor memory cell has been altered to provide the capacitor in a vertical dimension. In such designs, the capacitor has been formed in a trench in the surface of the semiconductor substrate. In yet denser designs, other forms of capacitor design are proposed, such as stacking the capacitor above the transfer device. Additional designs have been proposed in which the device and its associated capacitor are formed within a trench of preferably minimum dimension.
While such design approaches appear to allow progressive increases in density in the near future, they are constrained by the limit of one memory cell per minimum photolithographic dimension. If semiconductor technology is to be extendable, design and process techniques are required which will enable full three-dimensional circuit design in which structural features are measured in tens of Angstroms and multiple circuit features are provided in the vertical dimension.
The world of three-dimensional semiconductor technology is not without precedent. For example, Kendall et al in U.S. Pat. No. 3,962,713 describes a three-dimensional capacitor structure formed by a series of vertical fins in the surface of a semiconductor substrate. The fins are oxidized and coated with a conductor to form the capacitor. Tigelaar et al in U.S. Pat. No. 4,827,323 describe a stacked capacitor for integrated circuit technology formed of a plurality of alternating conductor and dielectric layers in which alternate conductive layers are interconnected at their edges by a pair of vertical conductors.
Various additional 3-dimensional processing features are also known. For example, U.S. Pat. No. 4,764,801 to McLaughlin et al teaches the use of pillar-shaped vertical epitaxial and polysilicon regions interconnected by a plurality of substantially planar, isolated polysilicon layers to form various device structures. U.S. Pat. No. 4,597,003 to Aine et al is also of interest, as it teaches semiconductor etching techniques for forming thin free-standing layers of n-type silicon on the opposite faces of a semiconductor wafer by the preferential etching of p-type semiconductor material.
Several 3-dimensional semiconductor device structures have been proposed with little or no process or fabrication detail. Both U.S. Pat. No. 4,794,442 to Warner et al. and Published European Application 73,486 of Toyama are examples. The former describes 3-dimensional semiconductor structures formed without metals or insulators through the use of molecular beam deposited epitaxial layers and regions. Device sizes rival conventional planar devices and have dimensions in the 10+ micron range. The latter describes the formation of a multi-level DRAM formed of slabs of semiconductor material including a plurality of memory cells and circuit interconnection means stacked to form a cube-like structure.
Additional three-dimensional semiconductor structures have been described. For example, U.S. Pat. No. 4,675,980 to Lade et al describes a layered device in which layers of insulator and metal are used to form a MOMOM tunnel device U.S. Pat. No. 4,763,179 to Tsubouchi et al describes a DRAM cell in which a buried capacitor is formed by enlarging a trench below the surface of a semiconductor wafer by the selective etching of a dopant introduced into the trench.